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Copyright, ii
Preface, xiii
Chapter 1. Digital Systems and Information, 3
1-1. Information Representation, 4
The Digital Computer, 6
Beyond the Computer, 7
More on the Generic Computer, 11
1-2. Number Systems, 13
Binary Numbers, 14
Octal and Hexadecimal Numbers, 16
Number Ranges, 17
1-3. Arithmetic Operations, 18
Conversion from Decimal to Other Bases, 20
1-4. Decimal Codes, 23
BCD Addition, 24
1-5. Alphanumeric Codes, 25
ASCII Character Code, 26
Parity Bit, 26
1-6. Gray Codes, 28
1-7. Chapter Summary, 31
References, 31
Problems, 31
Chapter 2. Combinational Logic Circuits, 35
2-1. Binary Logic and Gates, 35
Binary Logic, 36
Logic Gates, 38
2-2. Boolean Algebra, 39
Basic Identities of Boolean Algebra, 42
Algebraic Manipulation, 44
Complement of a Function, 47
2-3. Standard Forms, 48
Minterms and Maxterms, 49
Sum of Products, 52
Product of Sums, 54
2-4. Two-Level Circuit Optimization, 54
Cost Criteria, 55
Map Structures, 56
Two-Variable Maps, 59
Three-Variable Maps, 61
2-5. Map Manipulation, 65
Essential Prime Implicants, 65
Nonessential Prime Implicants, 67
Product-of-Sums Optimization, 68
Don’t-Care Conditions, 70
2-6. Pragmatic Two-Level Optimization, 72
2-7. Multiple-Level Circuit Optimization, 76
2-8. Other Gate Types, 81
2-9. Exclusive-OR Operator and Gates, 85
Odd Function, 86
2-10. High-Impedance Outputs, 88
2-11. Chapter Summary, 90
References, 90
Problems, 91
Chapter 3. Combinational Logic Design, 97
3-1. Design Procedure, 97
3-2. Beginning Hierarchical Design, 104
3-3. Technology Mapping, 107
3-4. Verification, 111
Manual Logic Analysis, 111
Simulation, 113
3-5. Combinational Functional Blocks, 113
3-6. Rudimentary Logic Functions, 115
Value-Fixing, Transferring, and Inverting, 115
Multiple-Bit Functions, 116
Enabling, 119
3-7. Decoding, 121
Decoder and Enabling Combinations, 124
Decoder-Based Combinational Circuits, 126
3-8. Encoding, 127
Priority Encoder, 129
Encoder Expansion, 130
3-9. Selecting, 131
Multiplexers, 131
Multiplexer-Based Combinational Circuits, 136
3-10. Chapter Summary, 138
References, 140
Problems, 140
Chapter 4. Arithmetic Functions and HDLs, 149
4-1. Iterative Combinational Circuits, 150
4-2. Binary Adders, 151
Half Adder, 151
Full Adder, 152
Binary Ripple Carry Adder, 153
4-3. Binary Subtraction, 155
Complements, 157
Subtraction Using 2s Complement, 158
4-4. Binary Adder–Subtractors, 159
Signed Binary Numbers, 161
Signed Binary Addition and Subtraction, 163
Overflow, 165
4-5. Other Arithmetic Functions, 167
Contraction, 167
Incrementing, 169
Decrementing, 170
Multiplication by Constants, 170
Division by Constants, 172
Zero Fill and Extension, 172
4-6. Hardware Description Languages, 173
Hardware Description Languages, 173
Logic Synthesis, 175
4-7. HDL Representations—VHDL, 176
Behavioral Description, 186
4-8. HDL Representations—Verilog, 187
Behavioral Description, 195
4-9. Chapter Summary, 196
References, 196
Problems, 197
Chapter 5. Sequential Circuits, 207
5-1. Sequential Circuit Definitions, 208
5-2. Latches, 210
SR and SR Latches, 211
D Latch, 214
5-3. Flip-Flops, 215
Master–Slave Flip-Flops, 216
Edge-Triggered Flip-Flop, 218
Standard Graphics Symbols, 219
Direct Inputs, 221
5-4. Sequential Circuit Analysis, 222
Input Equations, 223
State Table, 224
State Diagram, 227
Sequential Circuit Simulation, 229
5-5. Sequential Circuit Design, 230
Design Procedure, 231
Finding State Diagrams and State Tables, 231
State Assignment, 238
Designing with D Flip-Flops, 240
Designing with Unused States, 243
Verification, 245
5-6. Other Flip-Flop Types, 247
JK and T Flip-Flops, 247
5-7. State-Machine Diagrams and Applications, 250
State-Machine Diagram Model, 250
Constraints on Input Conditions, 253
Design Applications Using State-Machine Diagrams, 256
5-8. HDL Representation for Sequential Circuits—VHDL, 264
5-9. HDL Representation for Sequential Circuits—Verilog, 272
5-10. Chapter Summary, 278
References, 279
Problems, 280
Chapter 6. Selected Design Topics, 295
6-1. The Design Space, 295
Integrated Circuits, 296
CMOS Circuit Technology, 296
Technology Parameters, 302
6-2. Gate Propagation Delay, 304
6-3. Flip-Flop Timing, 306
6-4. Sequential Circuit Timing, 308
6-5. Asynchronous Interactions, 310
6-6. Synchronization and Metastability, 312
6-7. Synchronous Circuit Pitfalls, 318
6-8. Programmable Implementation Technologies, 319
Read-Only Memory, 322
Programmable Logic Array, 323
Programmable Array Logic Devices, 327
6-9. Chapter Summary, 329
References, 329
Problems, 330
Chapter 7. Registers and Register Transfers, 335
7-1. Registers and Load Enable, 336
Register with Parallel Load, 337
7-2. Register Transfers, 339
7-3. Register Transfer Operations, 341
7-4. A Note for VHDL and Verilog Users Only, 344
7-5. Microoperations, 344
Arithmetic Microoperations, 345
Logic Microoperations, 347
Shift Microoperations, 349
7-6. Microoperations on a Single Register, 350
Multiplexer-Based Transfers, 350
Shift Registers, 353
Ripple Counter, 357
Synchronous Binary Counters, 359
Other Counters, 363
7-7. Register-Cell Design, 366
7-8. Multiplexer and Bus-Based Transfers for Multiple Registers, 372
Three-State Bus, 374
7-9. Serial Transfer and Microoperations, 375
Serial Addition, 377
7-10. Control of Register Transfers, 378
Design Procedure, 380
7-11. HDL Representation for Shift Registers and Counters—VHDL, 395
7-12. HDL Representation for Shift Registers and Counters—Verilog, 398
7-13. Microprogrammed Control, 399
7-14. Chapter Summary, 402
References, 402
Problems, 402
Chapter 8. Memory Basics, 413
8-1. Memory Definitions, 413
8-2. Random-Access Memory, 414
Write and Read Operations, 416
Timing Waveforms, 417
Properties of Memory, 419
8-3. SRAM Integrated Circuits, 419
Coincident Selection, 422
8-4. Array of SRAM ICs, 425
8-5. DRAM ICs, 429
DRAM Cell, 429
DRAM Bit Slice, 431
8-6. DRAM Types, 435
Synchronous DRAM (SDRAM), 436
Double-Data-Rate SDRAM (DDR SDRAM), 439
RAMBUS^® DRAM (RDRAM), 439
8-7. Arrays of Dynamic RAM ICs, 440
8-8. Chapter Summary, 441
References, 441
Problems, 441
Chapter 9. Computer Design Basics, 443
9-1. Introduction, 444
9-2. Datapaths, 444
9-3. The Arithmetic/Logic Unit, 447
Arithmetic Circuit, 448
Logic Circuit, 450
Arithmetic/Logic Unit, 451
9-4. The Shifter, 453
Barrel Shifter, 454
9-5. Datapath Representation, 455
9-6. The Control Word, 458
9-7. A Simple Computer Architecture, 464
Instruction Set Architecture, 464
Storage Resources, 465
Instruction Formats, 466
Instruction Specifications, 468
9-8. Single-Cycle Hardwired Control, 471
Instruction Decoder, 472
Sample Instructions and Program, 474
Single-Cycle Computer Issues, 477
9-9. Multiple-Cycle Hardwired Control, 478
Sequential Control Design, 482
9-10. Chapter Summary, 489
References, 490
Problems, 490
Chapter 10. Instruction Set Architecture, 497
10-1. Computer Architecture Concepts, 497
Basic Computer Operation Cycle, 498
Register Set, 499
10-2. Operand Addressing, 499
Three-Address Instructions, 500
Two-Address Instructions, 501
One-Address Instructions, 501
Zero-Address Instructions, 502
Addressing Architectures, 503
10-3. Addressing Modes, 506
Implied Mode, 507
Immediate Mode, 507
Register and Register-Indirect Modes, 508
Direct Addressing Mode, 508
Indirect Addressing Mode, 510
Relative Addressing Mode, 510
Indexed Addressing Mode, 511
Summary of Addressing Modes, 511
10-4. Instruction Set Architectures, 513
10-5. Data-Transfer Instructions, 514
Stack Instructions, 515
Independent versus Memory-Mapped I/O, 517
10-6. Data-Manipulation Instructions, 518
Arithmetic Instructions, 518
Logical and Bit-Manipulation Instructions, 519
Shift Instructions, 520
10-7. Floating-Point Computations, 522
Arithmetic Operations, 523
Biased Exponent, 524
Standard Operand Format, 525
10-8. Program Control Instructions, 527
Conditional Branch Instructions, 528
Procedure Call and Return Instructions, 530
10-9. Program Interrupt, 531
Types of Interrupts, 533
Processing External Interrupts, 534
10-10. Chapter Summary, 535
References, 536
Problems, 537
Chapter 11. RISC and CISC Central Processing Units, 543
11-1. Pipelined Datapath, 544
Execution of Pipeline Microoperations, 548
11-2. Pipelined Control, 549
Pipeline Programming and Performance, 551
11-3. The Reduced Instruction Set Computer, 553
Instruction Set Architecture, 554
Addressing Modes, 557
Datapath Organization, 557
Control Organization, 560
Data Hazards, 563
Control Hazards, 570
11-4. The Complex Instruction Set Computer, 574
ISA Modifications, 575
Datapath Modifications, 577
Control Unit Modifications, 577
Microprogrammed Control, 579
Microprograms for Complex Instructions, 582
11-5. More on Design, 586
Advanced CPU Concepts, 586
Recent Architectural Innovations, 589
11-6. Chapter Summary, 592
References, 593
Problems, 593
Chapter 12. Input–Output and Communication, 597
12-1. Computer I/O, 597
12-2. Sample Peripherals, 598
Keyboard, 598
Hard Drive, 599
Liquid Crystal Display Screen, 601
I/O Transfer Rates, 604
12-3. I/O Interfaces, 604
I/O Bus and Interface Unit, 605
Example of I/O Interface, 606
Strobing, 608
Handshaking, 609
12-4. Serial Communication, 611
Synchronous Transmission, 612
The Keyboard Revisited, 612
A Packet-Based Serial I/O Bus, 613
12-5. Modes of Transfer, 617
Example of Program-Controlled Transfer, 618
Interrupt-Initiated Transfer, 620
12-6. Priority Interrupt, 620
Daisy Chain Priority, 621
Parallel Priority Hardware, 623
12-7. Direct Memory Access, 624
DMA Controller, 625
DMA Transfer, 627
12-8. Chapter Summary, 628
References, 628
Problems, 629
Chapter 13. Memory Systems, 633
13-1. Memory Hierarchy, 633
13-2. Locality of Reference, 636
13-3. Cache Memory, 638
Cache Mappings, 640
Line Size, 645
Cache Loading, 647
Write Methods, 647
Integration of Concepts, 648
Instruction and Data Caches, 651
Multiple-Level Caches, 651
13-4. Virtual Memory, 652
Page Tables, 654
Translation Lookaside Buffer, 656
Virtual Memory and Cache, 658
13-5. Chapter Summary, 658
References, 659
Problems, 659
Index, 663

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